1. Field of the Invention
The present invention relates to a semiconductor memory and a method of operating a semiconductor memory.
2. Description of the Prior Art
In recent years, a nonvolatile semiconductor memory such as an EPROM (erasable and programmable read only memory) or an EEPROM (electrically erasable and programmable read only memory) is watched with interest as a semiconductor memory capable of substituting for a hard disk or a floppy disk serving as a magnetic memory.
In a memory cell of an EPROM or an EEPROM, carriers are stored in a floating gate electrode for storing data by presence/absence of the carriers and reading data by detecting change of a threshold voltage following presence/absence of carriers. In particular, the EEPROM includes a flash EEPROM erasing data in a memory cell array as a whole or dividing the memory cell array into arbitrary blocks and erasing data in units of the respective blocks. The flash EEPROM, also referred to as a flash memory, capable of attaining a large capacity, low power consumption and a high-speed operation with excellent impact resistance is applied to various types of portable apparatuses. Further, the flash EEPROM having memory cells each formed by a single transistor can be readily integrated as compared with the EEPROM.
In general, a stacked gate memory cell and a split gate memory cell are proposed for forming the flash EEPROM.
In a write operation of storing electrons in a floating gate electrode of the stacked gate memory cell, electrons contained in a channel of a semiconductor substrate are converted to hot electrons and injected into the floating gate electrode. At this time, a voltage of ten-odd volts must be applied to a control gate electrode. In an erase operation of extracting electrons stored in the floating gate electrode of the stacked gate memory cell, a Fowler-Nordheim tunnel current (hereinafter referred to as an FN tunnel current) is fed from a drain region to the floating gate electrode. At this time, a voltage of ten-odd volts must be applied to the drain region.
In a write operation of storing electrons in a floating gate electrode of the split gate memory cell, electrons contained in a channel of a semiconductor substrate are converted to hot electrons and injected into the floating gate electrode. At this time, a voltage of ten-odd volts must be applied to a drain region. In an erase operation of extracting electrons stored in the floating gate electrode of the split gate memory cell, an FN tunnel current is fed from a control gate electrode to the floating gate electrode. At this time, a voltage of ten-odd volts must be applied to the control gate electrode.
Thus, in the conventional stacked gate or split gate memory cell, electrons are injected into the floating gate electrode as hot electrons in the write operation, and the electrons stored in the floating gate electrode are extracted through the FN tunnel current in the erase operation.
In order to hold carriers stored in the floating gate electrode over a long period of time, the thickness of an insulator film enclosing the floating gate electrode must be increased. However, the electrons are injected into or extracted from the floating gate electrode as hot electrons or through the FN tunnel current. Therefore, the voltage (hereinafter referred to as the operating voltage of the memory cell) applied to the control gate electrode or the drain region in the write or erase operation must be increased as the thickness of the insulator film enclosing the floating gate electrode is increased.
A step-up circuit generates the operating voltage of the memory cell. In this case, the step-up circuit can practically generate a voltage of up to ten-odd volts. When employing a silicon oxide film as the insulator film enclosing the floating gate electrode, the thickness of this silicon oxide film cannot exceed 8 to 10 nm assuming that the operating voltage of the memory cell is ten-odd volts. In general, therefore, the thickness of the silicon oxide film employed as the insulator film enclosing the floating gate electrode is set to 8 to 10 nm, in order to suppress the operating voltage of the memory cell to ten-odd volts. When the thickness of the silicon oxide film is about 8 to 10 nm, electrons stored in the floating gate electrode can be held for a period practically satisfactory to some extent.
Also when storing holes in the floating gate electrode, the thickness of the silicon oxide film forming the insulator film enclosing the floating gate electrode is set to 8 to 10 nm similarly to the aforementioned case of storing electrons, thereby suppressing the operating voltage of the memory cell to ten-odd volts and holding the holes stored in the floating gate electrode for a period practically satisfactory to some extent.
The feature of the flash memory resides in that cells sharing a word line are temporarily subjected to batch erasing and thereafter subjected to rewriting. In relation to the memory cell array, a structure operable with a small number of contacts is employed in order to improve the degree of integration.
Recently, the flash EEPROM is also required to attain a lower voltage, operations at a higher speed, lower power consumption and higher integration while attaining a longer life by increasing the period for holding carriers stored in the floating gate electrode.
When forming the insulator film enclosing the floating gate electrode by the silicon oxide film having the thickness generally set to 8 to 10 nm as described above, the thickness of the silicon oxide film must not be reduced below 8 nm, in order to attain a long life.
When reducing the operating voltage of the memory cell, the time (lead time) for stepping up the voltage is so reduced that the write and erase operations can be performed at a higher speed. Further, power consumption can also be reduced.
The circuit scale of the step-up circuit for generating the operating voltage of the memory cell is increased as the generated voltage is increased. The occupied area (transistor size) of a transistor forming a peripheral circuit, such as a decoder, a sense amplifier or a buffer, of the flash EEPROM is increased on the substrate as the voltage resistance thereof is increased. When reducing the operating voltage of the memory cell, therefore, the circuit scale of the step-up circuit as well as the size of the transistor forming the peripheral circuit are reduced, whereby higher integration can be attained.
Thus, operations at a higher speed, lower power consumption and higher integration can be simultaneously implemented by reducing the operating voltage of the memory cell.
In the conventional stacked gate or split gate memory cell, however, electrons are injected into or extracted from the floating gate electrode as hot electrons or through the FN tunnel current. When employing the silicon oxide film as the insulator film enclosing the floating gate electrode, therefore, it is difficult to reduce the operating voltage of the memory cell beyond the current level while maintaining the thickness of the silicon oxide film at the current level of 8 to 10 nm. In other words, it is difficult to reduce the operating voltage of the memory cell while keeping the life of the conventional stacked gate or split gate memory cell at the current level without changing the structure thereof.
As described above, the feature of the flash memory resides in that the cells sharing a word line are subjected to batch erasing and thereafter subjected to rewriting. Therefore, the cells sharing the word line must be subjected to erasing and writing also when data may not be rewritten. In this case, the data are rewritten in two stages of erasing and writing. Therefore, it is difficult to perform writing on a group of cells forming a block (sector) subjected to batch erasing simultaneously with batch erasing or to perform the so-called overwriting performed in a magnetic disk. Thus, it is difficult to increase the speed for write and erase operations.
An object of the present invention is to provide a semiconductor memory capable of attaining a longer life, a lower voltage, operations at a higher speed, lower power consumption and a higher degree of integration.
Another object of the present invention is to implement the aforementioned semiconductor memory in a simple structure.
Still another object of the present invention is to further refine a first gate electrode and a second gate electrode and suppress dispersion of the gate lengths in the aforementioned semiconductor memory.
A further object of the present invention is to simultaneously perform erasing and writing in the aforementioned semiconductor memory.
A further object of the present invention is to provide a method of operating a semiconductor memory capable of readily operating the aforementioned semiconductor memory.
A semiconductor memory according to a first aspect of the present invention comprises a first gate electrode, a second gate electrode, a semiconductor region, a first insulator film formed on one surface of the semiconductor region and a second insulator film formed on another surface of the semiconductor region, for injecting carriers into the second gate electrode through the first insulator film, the semiconductor region and the second insulator film. In this case, the semiconductor region is preferably formed by a second conductivity type impurity region formed on a first layer consisting of a first conductivity type semiconductor. Preferably, the semiconductor region includes a second conductivity type semiconductor film formed on a first layer consisting of a first conductivity type semiconductor. In this case, the first gate electrode and the second gate electrode may be formed in a self-aligned manner.
A semiconductor memory according to a second aspect of the present invention comprises a second conductivity type first region and a second conductivity type second region formed on a first layer consisting of a first conductivity type semiconductor, a first gate electrode and a second gate electrode formed on the first layer between the first region and the second region, a second conductivity type third region formed on the first layer between the first gate electrode and the second gate electrode, a first insulator film formed between the first gate electrode and the third region and a second insulator film formed between the second gate electrode and the third region.
According to the present invention, therefore, the potential of the third region can be increased by simply applying a prescribed voltage to the second region for readily generating an electric field between the third region and the first gate electrode. Consequently, carriers permeating through a barrier of the insulator film located between the first gate electrode and the third region are accelerated by the electric field generated in the third region, to be injected into and stored in the second gate electrode beyond a barrier of the insulator film located between the third region and the second gate electrode. Therefore, data can be stored by presence/absence of carriers stored in the second gate electrode, and the semiconductor memory operates as a nonvolatile semiconductor memory.
In the aforementioned semiconductor memory according to the second aspect, the third region is preferably formed by a second conductivity type impurity region. Further, the third region may include a second conductivity type conductive film. In this case, the first gate electrode and the second gate electrode are preferably formed in a self-aligned manner.
It is preferable that the first gate electrode is formed through a first gate insulator film with respect to the first layer, and the second gate electrode is formed through a second gate insulator film with respect to the first layer.
It is preferable that the electrostatic capacitance between the second region and the second gate electrode is set larger than the electrostatic capacitance between the third region and the second gate electrode, and a voltage applied to the second region is transmitted to the second gate electrode by electrostatic coupling between the second region and the second gate electrode so that the third region connected with the second region through the first layer is substantially equalized in potential with the second region. Thus, the potential of the second gate electrode can be readily controlled by simply controlling the potential of the second region.
The width of the third region is preferably set substantially not more than the mean free path of carriers permeating through a barrier of the first insulator film located between the first gate electrode and the third region when having energy necessary for passing through a barrier of the second insulator film.
Thus, substantially all carriers permeating through the barrier of the first insulator film located between the first gate electrode and the third region acquire the energy for passing through the barrier of the second insulator film and turn into hot carriers, to be injected into the second gate electrode in an extremely high probability without remaining in the third region. Thus, the aforementioned functions of the present invention can be more reliably attained.
The second gate electrode is preferably formed on the side wall of the second region through a third insulator film. Thus, the areas of the overlapping portions of the second region and the second gate electrode can be readily increased for consequently increasing the electrostatic capacitance between the second region and the second gate electrode.
In this case, a groove may be formed in the first layer so that the second gate electrode is formed in the groove through the third insulator film on the side of the second region. Thus, the second gate electrode can be readily formed on the side wall of the second region.
In the aforementioned semiconductor memory according to the second aspect, it is preferable that a first conductivity type fourth region is formed on the second conductivity type second region, and the second region is formed on the overall region between the first layer and the fourth region.
Thus, the second region and the fourth region form a diode, so that a negative voltage can be readily applied to the second region and the fourth region having the diode structure without employing a complicated structure such as a conventional triple well structure. Therefore, positive and negative voltages can be employed for erase and write operations, and hence the maximum voltage generated in a step-up circuit can be substantially halved. Thus, voltage reduction can be attained and the scale of the step-up circuit can also be reduced, whereby higher integration can be attained. Further, the fourth region can be readily formed through a general process of implanting impurity ions, to result in no burden in the process.
There is a possibility that an excess current flows between the second region and the first layer when applying a negative voltage to the second region without employing the inventive diode structure, while an excess current may flow also between the first region and the second region (between a source and a drain) after erasing when either the first region or the second region is not floated after erasing. In this case, the excess current may disadvantageously exceed the allowable current quantity in the step-up circuit. According to the present invention, flow of such an excess current can be effectively prevented by employing the diode structure.
In this case, the fourth region is preferably capacitively coupled with the second gate electrode through a third insulator film. Thus, the voltage of the fourth region, which is directly applied from a power source through a wire, can be efficiently transmitted to the second gate electrode by capacitive coupling.
In the aforementioned semiconductor memory according to the second aspect, the first gate electrode preferably includes a side wall film formed in a self-aligned manner with respect to the third region. Thus, the first gate electrode can be formed with no problem of misalignment of a mask in a mask process.
In this case, the side wall film is preferably formed by depositing a first conductive film on the side surface of the third region and thereafter etching back the first conductive film. Thus, the gate length of the first gate electrode can be controlled through the thickness of the first conductive film, whereby the gate length can be reduced below the minimum limit size (minimum exposure size) in the mask process and controlled in higher precision than that in the mask process. Consequently, the first gate electrode can be more refined and dispersion of the gate length can be suppressed.
Preferably, the aforementioned semiconductor memory according to the second aspect further comprises a wire connected to the first region, and the wire is formed in a self-aligned manner with respect to the first region. Thus, the wire can be formed with no problem of misalignment of a mask in a mask process.
In this case, the wire is preferably formed by depositing a second conductive film on the side surface of the first gate electrode through a fourth insulator film and thereafter etching back the second conductive film. Thus, a wire insulated from the first gate electrode can be readily formed on the side portion of the first gate electrode in a self-aligned manner.
In the aforementioned semiconductor memory according to the second aspect, the third region is preferably formed by forming a side wall insulator film on the side surface of the first gate electrode in a self-aligned manner and thereafter etching back the first layer through the side wall insulator film. Thus, the third region can be formed in a self-aligned manner through the side wall insulator film formed in a self-aligned manner with no problem of misalignment of a mask in a mask process. Further, the third region can be formed in a small width below the minimum limit size in the mask process by controlling the thickness of the insulator film for forming the side wall insulator film. In addition, the width of the side wall insulator film can be precisely controlled by controlling the thickness of the insulator film for forming the side wall insulator film, whereby the width of the third region formed through the side wall insulator film can also be precisely controlled. Consequently, the third region can be more refined and dispersion of the width of the third region can be suppressed.
It is preferable that the first gate electrode and the second gate electrode are formed on the major surface of the first layer and the third region consisting of the conductive film is formed between the first gate electrode and the second gate electrode on the major surface of the first layer. When forming the first gate electrode, the second gate electrode and the third region on the first layer in the aforementioned manner, no grooves may be formed in the first layer for embedding the first gate electrode, the second gate electrode and the third region. Therefore, the structure can be simplified as compared with the case of forming such grooves, and the inventive semiconductor memory can consequently be implemented in a simple structure. Further, the first layer may not be formed with grooves and hence the structure having the first gate electrode, the third region and the second gate electrode can be formed through a simple process. In addition, no tunnel insulator film or the like may be formed on the side surface of the first layer damaged by etching for forming such grooves, whereby the quality of a tunnel insulator film is not deteriorated.
In this case, it is preferable that at least part of the third region is formed on the upper surface of the second gate electrode, and at least part of the first gate electrode is formed on the upper surface of the third region. Thus, a structure requiring no grooves in the first layer can be readily obtained by vertically arranging the first gate electrode, the second gate electrode and the third region.
The third region preferably includes a single-crystalline silicon film. Thus, the first insulator film can be formed by oxidizing the single-crystalline silicon film, whereby the first insulator film can be obtained with excellent film quality.
The third region may include a first side wall film consisting of a first conductive film formed in a self-aligned manner. Thus, the third region consisting of the first conductive film can be formed with no problem of misalignment of a mask in a mask process.
In this case, the first side wall film consisting of the first conductive film preferably includes a second side wall film consisting of a second conductive film formed on the side wall of the second gate electrode through the second insulator film and a third side wall film consisting of a third conductive film formed to be in contact with the side surface of the second side wall film and the surface of the first layer. Thus, the third side wall film can connect the third region and the first layer with each other thereby connecting the third region with the second region through the first layer. Thus, the aforementioned functions of the present invention can be more reliably attained.
In this case, it is preferable that the second side wall film is formed by depositing a second conductive film on the side surface of the second gate electrode through the second insulator film and thereafter etching back the second conductive film, and the third side wall film is formed by depositing a third conductive film to cover the first layer and the second side wall film and thereafter etching back the third conductive film, to be in contact with the side surface of the second side wall film and the surface of the first layer.
Thus, the thicknesses of the second side wall film and the third side wall film can be controlled by the thicknesses of the second conductive film and the third conductive film respectively, whereby the third region consisting of the second side wall film and the third side wall film can be formed in a small width below the minimum limit size (minimum exposure size) in the mask process. Further, the widths of the second and third side wall films can be precisely controlled by controlling the widths of the second and third conductive films, whereby the width of the third region consisting of the second and third side wall films can also be precisely controlled. Consequently, the third region can be more refined and dispersion of the width of the third region can be suppressed.
The second region preferably includes a fourth side wall film consisting of a fourth conductive film formed on the side surface of the second gate electrode in a self-aligned manner through a third insulator film. Thus, the fourth side wall film can increase the opposite areas of the second region and the second gate electrode. Therefore, the electrostatic capacitance between the second region and the second gate electrode can be readily increased. Consequently, the electrostatic capacitance between the second region and the second gate electrode can be readily increased beyond the electrostatic capacitance between the third region and the second gate electrode. Therefore, the potential of the second gate electrode can be readily controlled by varying the voltage applied to the second region.
In this case, the fourth side wall film preferably includes a fifth side wall film consisting of a fifth conductive film formed on the side wall of the second gate electrode through the third insulator film and a sixth side wall film consisting of a sixth conductive film formed to be in contact with the side surface of the fifth side wall film and the surface of the first layer. Thus, the sixth side wall film enables connection with the first layer, whereby the fifth and sixth side wall films can be readily connected with the second region consisting of the impurity region formed on the first layer. Consequently, the fifth and sixth side wall films can be readily employed as part of the second region.
The fourth side wall film defining the second region is preferably formed simultaneously with the first side wall film defining the third region. Thus, the fabrication process is not complicated also when providing the fourth side wall film.
It is preferable that the first region and the second region are so formed on the first layer as to expose the side surfaces thereof, the first gate electrode includes a seventh side wall film formed on the side surface of the first region in a self-aligned manner through a third insulator film, and the second gate electrode includes an eighth side wall film formed on the side surface of the second region in a self-aligned manner through a fourth insulator film.
Thus, the gate lengths of the first gate electrode and the second gate electrode can be controlled by the thickness of the deposited conductive film and hence the gate lengths can be reduced below the minimum limit size (minimum exposure size) in a mask process and controlled in higher precision than that in the mask process. Consequently, the first gate electrode and the second gate electrode can be more refined and dispersion of the gate lengths can be suppressed.
In this case, the seventh side wall film and the eighth side wall film are preferably simultaneously formed by depositing a seventh conductive film to cover the overall surface and thereafter etching back the seventh conductive film. Thus, the first gate electrode and the second gate electrode are simultaneously formed so that the fabrication process can be simplified.
The third region consisting of the conductive film may be formed in a self-aligned manner with respect to the first gate electrode and the second gate electrode. Thus, the third region can be formed in addition to the first gate electrode and the second gate electrode with no problem of misalignment of a mask in a mask process.
In this case, the third region is preferably formed to fill up a clearance between the seventh side wall film and the eighth side wall film. Thus, the third region can be readily formed in a self-aligned manner.
The thickness of the first insulator film is preferably smaller than the thickness of the second insulator film. Thus, a barrier of the first insulator film on the side of the first gate electrode for extracting carriers can be reduced in thickness for readily extracting the carriers from the first gate electrode. Further, the carriers stored in the second gate electrode can be held over a long period of time with the thick second insulator film on the side of the second gate electrode.
In this case, the first insulator film and the second insulator film are preferably formed by introducing an impurity suppressing oxidation into the first gate electrode while introducing an impurity prompting oxidation into the second gate electrode and thereafter oxidizing the first gate electrode and the second gate electrode respectively. Thus, the second insulator film and the first insulator film having a smaller thickness than the second insulator film can be simultaneously formed through a single oxidation step.
Preferably, a fifth insulator film is formed between the upper surface of the third region located between the first gate electrode and the second gate electrode and the upper side surfaces of the first gate electrode and the second gate electrode. Thus, the fifth insulator film can reliably insulate the first gate electrode and the second gate electrode from the third region.
A semiconductor memory according to a third aspect of the present invention comprises a second conductivity type region formed on a first layer consisting of a first conductivity type semiconductor, a gate electrode and a semiconductor region formed between the second conductivity type region and the gate electrode through insulator films respectively. Carriers are injected into the gate electrode from the second conductivity type region through the insulator films and the semiconductor region. The operation of injecting carriers includes not only injection of electrons but also extraction of electrons. In this case, the semiconductor region preferably consists of a second conductivity type impurity region formed on the first layer consisting of the first conductivity type semiconductor.
A semiconductor memory according to a fourth aspect of the present invention comprises a second conductivity type first region and a second conductivity type second region formed on a first layer consisting of a first conductivity type semiconductor, a first gate electrode formed on the first layer, a second gate electrode formed on the first layer between the first region and the second region, a second conductivity type third region formed between either the first gate electrode or the second region on the first layer and the second gate electrode, a first insulator film formed on one surface of the third region and a second insulator film formed on another surface of the third region.
According to the present invention, therefore, the potential of the third region can be increased by applying a prescribed voltage to the first gate electrode or the second region thereby readily generating an electric field between the third region and the first gate electrode or the second region. Consequently, carriers permeating through a barrier of the insulator film located between the first gate electrode or the second region and the third region are accelerated by the electric field generated in the third region to be injected into (written in) and stored in the second gate electrode through the barrier of the insulator film located between the third region and the second gate electrode. Therefore, data can be stored by presence/absence of the carriers stored in the second gate electrode, and the semiconductor memory operates as a nonvolatile semiconductor memory.
In this case, it is preferable that the semiconductor memory further comprises a third insulator film formed between the second gate electrode and the first region, the first gate electrode extends in a direction intersecting with the first region and the second region, the first insulator film is formed between the third region and the second region, and the second insulator film is formed between the third region and the second gate electrode. This structure is hereinafter referred to as a structure 1.
When employing the structure 1, the potential of the third region can be increased by applying a positive voltage to the first region and the first gate electrode and a negative voltage to the second region, thereby readily generating an electric field between the third region and the second region. Consequently, carriers permeating through a barrier of the first insulator film located between the second region and the third region are accelerated by the electric field generated in the third region to be injected into (written in) and stored in the second gate electrode through the barrier of the second insulator film located between the third region and the second gate electrode. Therefore, data can be stored by presence/absence of the carriers stored in the second gate electrode, and the semiconductor memory operates as a nonvolatile semiconductor memory. As to a memory cell subjected to erasing, a negative voltage is applied to the first gate electrode thereby extracting the electrons stored in the second gate electrode toward the first region for performing erasing.
According to this structure 1, write and erase operations can be controlled only with a positive/negative voltage applied to the first gate electrode. Thus, batch rewriting is enabled for simultaneously performing erasing and writing on about 1000 to 4000 memory cells connected to a plurality of first gate electrodes respectively, which are subjected to writing after batch erasing in the conventional flash memory.
In the aforementioned semiconductor memory according to the structure 1, the second gate electrode is preferably formed through a gate insulator film with respect to the first layer. Thus, the second gate electrode can be operated as the gate of a transistor in the write operation.
In the aforementioned semiconductor memory according to the structure 1, the electrostatic capacitance between the first gate electrode and the second gate electrode is set larger than the electrostatic capacitance of the remaining parts, and a voltage applied to the first gate electrode is transmitted to the second gate electrode by electrostatic coupling between the first gate electrode and the second gate electrode so that the third region connected with the first region through the first layer is substantially equalized in potential with the first region. Thus, the potential of the second gate electrode can be readily controlled by simply controlling the potential of the first gate electrode.
In the aforementioned semiconductor memory according to the structure 1, the third region and the second region are preferably connected through a diode such as a p-n junction diode or a Schottky barrier diode. Thus, the potential difference between the second region and the third region can be held when a negative voltage is applied to the second region and a positive or ground voltage is transmitted to the third region in writing. When a positive voltage is applied to the second region in reading, on the other hand, a current can be fed between the second region and the third region with no or low resistance.
In the aforementioned semiconductor memory according to the structure 1, the second region may include a material having a Schottky barrier with respect to silicon. Thus, potential difference is held between the third region and the second region due to the Schottky barrier, whereby electrons can be accelerated. Further, the Schottky barrier has a relatively low level of about 0.5 eV, and hence a large quantity of electrons can be extracted from the second region also when the potential difference between the second and third regions is small. In this case, the first insulator film preferably has the smallest possible thickness within the range stabilizing the interface between the second region and the third region. Thus, the thickness of a barrier formed by the first insulator film can be reduced by reducing the thickness of the first insulator film, so that the first insulator film can be prevented from influencing the Schottky barrier characteristic. At the same time, the first insulator film can readily stabilize the interface between the second region and the third region readily unstabilized due to generation of a large number of interfacial levels.
The thickness of the Schottky barrier can be precisely controlled with the impurity concentration of the third region. In this case, a potential gradient can be provided on the third region by lowering the impurity concentration of the third region. Thus, the electrons extracted from the second region can be gradually accelerated and supplied with energy for passing through a barrier of an oxide film immediately before injection into the second gate electrode. Thus, the electrons are transported to a portion close to the second gate electrode in a low energy state with a long mean free path and further accelerated to be injected into the second gate electrode, to hardly lose energy in the course of the process. Consequently, the electrons are injected into the second gate electrode with a high probability.
In this case, an insulator film located between the second region and the first layer preferably has a thickness capable of insulating the second region and the first layer from each other. Thus, also when the third region and the second region are reverse-biased through the Schottky barrier and the second region and the first layer are forward-biased, the insulator film can sufficiently insulate the second region and the first layer from each other.
In the aforementioned semiconductor memory according to the structure 1, the width of the third region is preferably set substantially not more than the mean free path of carriers permeating through a barrier of the first insulator film located between the second region and the third region when having energy necessary for passing through a barrier of the second insulator film. Thus, almost all carriers permeating through the barrier of the first insulator film located between the second region and the third region acquire energy for passing through the barrier of the second insulator film and turn into hot carriers, to be injected into the second gate electrode in an extremely high probability without remaining in the third region. Therefore, the aforementioned functions of the present invention can be more reliably attained.
A method of operating a semiconductor memory according to a fifth aspect of the present invention is a method of operating a semiconductor memory comprising a second conductivity type first region and a second conductivity type second region formed on a first layer consisting of a first conductivity type semiconductor, a first gate electrode formed on the first layer between the first region and the second region through a first gate insulator film with respect to the first layer, a second gate electrode formed on the first layer between the first region and the second region through a second gate insulator film with respect to the first layer, a second conductivity type third region formed on the first layer between the first gate electrode and the second gate electrode, a first insulator film formed between the first gate electrode and the third region and a second insulator film formed between the second gate electrode and the third region, for writing data by injecting hot carriers into the second gate electrode from the first gate electrode through the first insulator film, the third region and the second insulator film.
In an initial stage of a write operation, prescribed potential difference is caused between the first gate electrode and the third region and between the first gate electrode and the second gate electrode, for continuously performing writing. Hot carriers are continuously injected into the second gate electrode as the write operation progresses, so that the potential of the second gate electrode gradually lowers from the initial value. The potential of the third region also lowers along with reduction of the potential of the second gate electrode, so that the potential difference between the first gate electrode and the third region finally lowers below a prescribed value. Thus, the hot carriers contained in the first gate electrode cannot permeate through the barrier of the second insulator film even if the hot carriers contained in the first gate electrode can permeate through the barrier of the first insulator film, to automatically terminate the write operation.
In the aforementioned method of operating a semiconductor device according to the fifth aspect, data of at least three values may be written by varying the initial field intensity between the first gate electrode and the third region thereby controlling the quantity of the hot carriers injected into the second gate electrode. Thus, multivalued data can be stored in a single semiconductor memory.
It is preferable to erase data by extracting the hot carriers from the second gate electrode to the third region through the second insulator film.
The electrostatic capacitance between the second region and the second gate electrode is preferably set larger than the electrostatic capacitance between the third region and the second gate electrode, and a voltage applied to the second region is preferably transmitted to the second gate electrode by electrostatic coupling between the second region and the second gate electrode so that the third region connected with the second region through the first layer is substantially equalized in potential with the second region. Thus, the potential of the second gate electrode can be readily controlled by simply controlling the potential of the second region.
The width of the third region is preferably set substantially not more than the mean free path of carriers permeating through a barrier of the first insulator film located between the first gate electrode and the third region when having energy necessary for passing through a barrier of the second insulator film.
Thus, almost all carriers permeating through the barrier of the first insulator film located between the first gate electrode and the third region acquire energy for passing through the barrier of the second insulator film and turn into hot carriers, to be injected into the second gate electrode in an extremely high probability without remaining in the third region. Therefore, the aforementioned functions of the present invention can be more reliably attained.
When erasing data, it is preferable to temporarily set the voltage of the second region coupled with the second gate electrode to a prescribed value and thereafter hold the second region in an open state.
In an initial stage of an erase operation, prescribed potential difference is caused between the second gate electrode and the third region, for continuously performing erasing. The potential of the second gate electrode gradually rises as the erase operation progresses. When the potential difference between the second gate electrode and the third region is less than a prescribed value, electrons contained in the second gate electrode cannot permeate through the barrier of the second insulator film, not to further perform the erase operation. Thus, the erase operation is automatically terminated.
A method of operating a semiconductor memory according to a sixth aspect of the present invention is a method of operating a semiconductor memory comprising a second conductivity type first region and a second conductivity type second region formed on a first layer consisting of a first conductivity type semiconductor, a first gate electrode formed on the first layer, a second gate electrode formed on the first layer between the first region and the second region through a gate insulator film with respect to the first layer, a second conductivity type third region formed between either the first gate electrode or the second region on the first layer and the second gate electrode, a first insulator film formed on one surface of the third region and a second insulator film formed on another surface of the third region, for writing data by injecting hot carriers from either the first gate electrode or the second region into the second gate electrode through the first insulator film, the third region and the second insulator film.
In an initial stage of a write operation, prescribed potential difference is caused between the first gate electrode or the second region and the third region and between the first gate electrode or the second region and the second gate electrode, for continuously performing writing. Hot carriers are continuously injected into the second gate electrode as the write operation progresses, so that the potential of the second gate electrode gradually lowers from the initial value. The potential of the third region also lowers along with reduction of the potential of the second gate electrode, so that the potential difference between the first gate electrode or the second region and the third region finally lowers below a prescribed value. Thus, the hot carriers contained in the first gate electrode or the second region cannot permeate through the barrier of the second insulator film even if the hot carriers contained in the first gate electrode or the second region can permeate through the barrier of the first insulator film, to automatically terminate the write operation.
In the method of operating a semiconductor memory according to the sixth aspect of the present invention, it is preferable to erase data by extracting the hot carriers from the second gate electrode to the first region through a third insulator film.
In the aforementioned method of operating a semiconductor memory according to the sixth aspect, the electrostatic capacitance between the first gate electrode and the second gate electrode is set larger than the electrostatic capacitance of the remaining parts, and a voltage applied to the first gate electrode is transmitted to the second gate electrode by electrostatic coupling between the first gate electrode and the second gate electrode so that the third region connected with the first region through said first layer is substantially equalized in potential with the first region. Thus, the potential of the second gate electrode can be readily controlled by simply controlling the potential of the first gate electrode.
In the aforementioned method of operating a semiconductor memory according to the sixth aspect, the width of the third region is preferably set substantially not more than the mean free path of carriers permeating through a barrier of the first insulator film located between the second region and the third region when having energy necessary for passing through a barrier of the second insulator film.
Thus, almost all carriers permeating through the barrier of the first insulator film located between the second region and the third region acquire energy for passing through the barrier of the second insulator film and turn into hot carriers, to be injected into the second gate electrode in an extremely high probability without remaining in the third region. Therefore, the aforementioned functions of the present invention can be more reliably attained.
In the aforementioned method of operating a semiconductor memory according to the sixth aspect, it is preferable to apply a positive voltage and a negative voltage to the first region and the second region respectively while applying a negative voltage and a positive voltage to the first gate electrode of a memory cell subjected to erasing and the first gate electrode of a memory cell subjected to writing respectively when rewriting data thereby simultaneously performing erasing and writing on a plurality of memory cells connected with a plurality of first gate electrodes respectively and holding data as such as to a memory cell requiring no data change.
Thus, batch rewriting is enabled for simultaneously performing erasing and writing on 1000 to 4000 memory cells connected to a plurality of first gate electrodes respectively, which are subjected to batch erasing and thereafter to writing in the conventional flash memory. Further, a memory cell requiring no rewriting automatically holds data as such without erasing the data and newly rewriting the same data, whereby stress on a tunnel insulator film reduces. Thus, the life of the tunnel insulator film is increased and the number of rewriting times can consequently be increased.
In the aforementioned method of operating a semiconductor memory according to the sixth aspect, the voltage of the first gate electrode coupled with the second gate electrode may be temporarily set to a prescribed negative potential for thereafter returning the potential of the first gate electrode to a potential set as a ground potential or a neutral potential when erasing data.
Thus, weak writing is caused so that overerasing can be corrected. When overerasing is performed until the second gate electrode reaches a positive potential exceeding the threshold voltage and the first gate electrode is returned to a potential set as a ground potential (0 V) or a neutral potential, the potential difference between the second gate electrode and the first region first reduces to terminate erasing. A transistor located under the second gate electrode is turned on. Thus, the potential of the third region increases. In this case, a negative voltage is applied to the second region to cause potential difference between the third region and the second region, and electrons are consequently injected from the second region into the second gate electrode for performing weak writing. Thus, overerasing can be corrected.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.